In-situ strip process for polysilicon etching in deep sub-micron technology

ABSTRACT

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF 4  gas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to a method of fabricating semiconductorstructures, and more particularly, to a method of patterning apolysilicon layer in the manufacture of an integrated circuit device.

(2) Description of the Prior Art

Polysilicon pattern definition remains a significant challenge insemiconductor manufacturing. The minimum width of the polysilicon layerdetermines the minimum transistor length of MOS technologies. Transistorswitching speed and packing density depend heavily on the ability toreliably and repeatably manufacture transistors with very narrowpolysilicon gates.

Referring now to FIG. 1, a cross-section of a partially completed priorart integrated circuit device is shown. A gate oxide layer 14 overlies asemiconductor substrate 10. A polysilicon layer 18 overlies the gateoxide layer 14. A hard mask layer 22 overlies the polysilicon layer 18.Finally, a photoresist layer 26 overlies the hard mask layer 22. Notethat the photoresist layer 26 has been patterned by, for example, aphotolithographic sequence of coating, exposure, and development.

Referring now to FIG. 7, the polysilicon layer 18 is patterned using theprior art sequence that is illustrated by the process flow chart. Note,first, that the prior art process etches the pattern of the photoresistlayer 26 into the hard mask layer 22 in step 30. Second, the photoresistlayer 26 is stripped away in step 34. Third, the pattern of the hardmask layer 22 is etched into the polysilicon layer 18 in step 38.Finally, the hard mask layer 22 is stripped away in step 42. Note thatan intervening resist strip (step 34) necessitates the removal of thewafers from the etching chamber between the hard mask etch (step 30) andthe gate etch (step 38).

Referring now to FIG. 2 and to FIG. 7, step 30, the photoresist layer 26may be trimmed. This trimming step is performed to reduce the width ofthe photoresist layer 26 to a dimension that is smaller than thecapability of the photolithographic exposure equipment. This trimmingetch is performed in the plasma dry etch chamber and reduces the widthof the patterned photoresist layer 26 to a dimension that will enablethe final patterned polysilicon layer 18 to meet the critical dimension(CD) specifications for the manufacturing process.

Referring now to FIG. 3 and to FIG. 7, step 30, the pattern of thephotoresist layer 26 is etched into the hard mask layer 22. This etchingstep is again performed in the plasma dry etch chamber.

Referring now to FIG. 4 and to FIG. 7, step 34, the photoresist layer 26is stripped away. This photoresist layer 26 must be removed to improvethe selectivity of the plasma dry etch process. Because the gate oxidelayer 14 of the deep sub-micron process is very thin, the subsequentpolysilicon etching step must have a high selectivity to the gate oxide.Removing the photoresist layer 26 prior to the polysilicon etch step 38improves this selectivity. This is the reason that the hard mask layer22 is used.

Of particular importance to the present invention is the fact that thesemiconductor wafers must be removed from the plasma dry etch chamberduring photoresist stripping. A separate photoresist stripping chamberis typically used to strip away this remaining photoresist. Followingthe photoresist strip, the wafers are then returned to the plasma dryetch chamber for the gate or polysilicon layer 18 etch step 38. Thispolysilicon layer 18 is thereby etched in a photoresist free processthat is herein called an ex-situ process.

The additional wafer handling and process equipment required to removethe photoresist layer 26 increases the cycle time and the processingcost. In addition, the wafers are open to increased contamination due tothe handling and the additional processing chamber. The additionalprocessing chamber also makes controlling processing parameters moredifficult. Finally, additional inspections and CD measurement steps maybe added to insure that the additional handling and process set-ups arewithin specification. This also adds to the processing cost and cycletime.

Referring now to FIG. 5 and to FIG. 7, step 38, the pattern of the hardmask layer 22 is etched into the polysilicon layer 18. This step isperformed in the plasma dry etch chamber after the photoresist stripstep 34.

Referring finally to FIG. 6 and to FIG. 7, step 42, the hard mask layeris stripped away to complete the patterning of the polysilicon layer 18.The wafers are removed from the plasma dry etch chamber for thisprocessing step 42. The hard mask stripping may comprise a wet etchprocess.

Several prior art approaches disclose methods to pattern polysilicon inthe manufacture to an integrated circuit device. U.S. Pat. No. 5,767,018to Bell teaches a method to etch a polysilicon pattern where ananti-reflective coating (ARC) is used. Pitting problems are eliminated.In one embodiment, a passivation layer is formed on the sidewalls of thepatterned ARC layer prior to polysilicon etching. In a secondembodiment, the passivation layer is formed on the ARC layer sidewallsduring the polysilicon etch. U.S. Pat. No. 6,037,266 to Tao et aldiscloses a method to etch a polysilicon pattern. A bottomanti-reflective coating (BARC) is used. The BARC layer and an oxidelayer are etched to form a pattern over the polysilicon layer. The BARClayer is then stripped away using a biased O₂ plasma. The polysiliconlayer is then etched using the oxide layer as a hard mask. U.S. Pat. No.5,346,586 to Keller teaches a method to etch a polysilicon pattern. Asilicide layer is used overlying the polysilicon layer. An oxide layeroverlies the silicide layer. The oxide layer is patterned using a hardmask layer. The photoresist layer is then removed using an ozone plasmastrip. The silicide layer is etched. Finally, the polysilicon layer isetched. U.S. Pat. No. 5,885,902 to Blasingame et al discloses a methodto etch an anti-reflective coating (ARC) layer using an inert gaseousplasma containing helium, nitrogen, or a mixture thereof.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide an effectiveand very manufacturable method of patterning a polysilicon layer in themanufacture of an integrated circuit device.

A further object of the present invention is to provide a method topattern the polysilicon layer that reduces process cycle time in theprocessing sequence.

Another further object of the present invention is to provide a methodto pattern the polysilicon layer that reduces wafer handling.

A yet further object of the present invention is to provide a method topattern the polysilicon layer by stripping away the photoresist layerin-situ to the polysilicon dry plasma etch chamber.

A still further object of the present invention is to provide a methodto eliminate photoresist polymer residue from the polysilicon dry etchchamber.

In accordance with the objects of this invention, a new method ofpatterning the polysilicon layer in the manufacture of an integratedcircuit device has been achieved. A polysilicon layer is providedoverlying a semiconductor substrate. The polysilicon layer may overlie agate oxide layer and would thereby comprise the polysilicon gate for MOSdevices. A hard mask layer is provided overlying the polysilicon layer.A resist layer is provided overlying the hard mask layer. The resistlayer is patterned to form a resist mask the exposes a part of the hardmask layer. The polysilicon layer is patterned in a plasma dry etchingchamber. First, the resist layer is optionally trimmed by etching.Second, the hard mask layer is etched where exposed by the resist maskto form a hard mask that exposes a part of the polysilicon layer. Third,the resist mask is stripped away. Fourth, polymer residue from theresist mask is cleaned away using a chemistry containing CF₄ gas. Fifth,the polysilicon layer is etched where exposed by the hard mask. Afterthe polysilicon layer is so patterned in the dry plasma etch chamber,the hard mask layer is stripped away to complete the patterning of thepolysilicon layer in the manufacture of the integrated circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIGS. 1 through 6 illustrate in cross-section a partially completedprior art integrated circuit device.

FIG. 7 illustrates the process flow sequence for the prior artpolysilicon patterning method.

FIG. 8 illustrates the process flow sequence for the preferredembodiment of the method of the present invention.

FIGS. 9 through 12 illustrate in cross-section the preferred embodimentof the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment discloses the application of the present invention to thepatterning of the polysilicon layer in the manufacture of an integratedcircuit device. It should be clear to those experienced in the art thatthe present invention can be applied and extended without deviating fromthe scope of the present invention.

Referring now particularly to FIG. 8, a process flow sequence for thepreferred embodiment of the present invention is shown. This processflow is of particular importance to the present invention. In thepreferred process flow, the resist trim etch, hard mask etch, resiststrip, and gate etch are combined into a single process step 50 within adry plasma etch chamber. The novel method allows these processingcomponents to be conducted using a continuous dry plasma etching recipethrough the sequential introduction of gases and control of parameters.The cost, time consumption, and contamination that are introduced by theexcessive wafer handling of the prior art process are therebyeliminated. After the polysilicon layer, herein called the gate, isetched, the wafers may be removed from the dry plasma etch chamber. Thehard mask layer is then stripped in step 54.

As in the prior art process, the resist trim step is optional to themethod of the invention. The resist trim step may be used to reduce theline width of the photoresist layer beyond the capability limits of thephotolithographic equipment.

Of particular importance to the process flow is in the inclusion withinthe etching step 50 of a polymer clean step. After the resist layer isstripped away, residual organic polymer from the resist material may bepresent in the chamber and on the sidewalls of the hard mask. A polymercleaning is therefore an essential aspect of the present invention. Theorganic polymer is removed using a cleaning chemistry containing CF₄gas. The chamber and the integrated circuit device is thereby cleaned ofresidual organic polymer material prior to the critical polysilicon gateetch.

Referring now to FIG. 9, a cross-section of the partially completeddevice of the present invention method is shown. A semiconductorsubstrate 60 is provided. The semiconductor substrate preferablycomprises monocrystalline silicon. A gate oxide layer 64 is providedoverlying the semiconductor substrate 60. The gate oxide layer 64 isvery thin in a deep sub-micron MOS process. For example, the gate oxidelayer 64 is formed by conventional means to about 20 Angstroms.

A polysilicon layer 68 is provided overlying the gate oxide layer 64.The polysilicon layer 68 may be doped or undoped and is formed byconventional means. As an example, the polysilicon of the preferredembodiment is undoped and has a thickness of between about 1,500Angstroms and 2,500 Angstroms.

A hard mask layer 72 is provided overlying the polysilicon layer 68. Thehard mask layer 72 will subsequently be patterned to form a hard maskoverlying the polysilicon layer 68 for the polysilicon etch step. Thehard mask layer 72 preferably comprises silicon oxynitride with athickness of between about 300 Angstroms and 500 Angstroms. Silicondioxide could be used as the hard mask layer 72 in the presentinvention.

A silicon dioxide layer 76 is provided overlying the hard mask layer 72.The silicon dioxide layer 76 is used as a buffer layer to gain etchingselectivity during the polysilicon etching. The silicon dioxide layer 76is optional to the present invention.

A resist layer 80 is provided overlying the silicon dioxide layer 76.The resist layer 80 preferably comprises a conventional photoresistmaterial that has been applied, exposed and developed to form a pattern.The resist layer 80 thereby contains the pattern that will betransferred, first, to the hard mask layer 72 and, second, to thepolysilicon layer 68. As an example, the preferred resist layer 80comprises a deep ultra-violet (DUV) photoresist, such as ShinEtsu 233DT.The photoresist material is spin coated overlying the wafer to athickness of between about 3,500 Angstroms and 5,000 Angstroms.Following bake, the resist layer has a thickness of between about 3,000Angstroms and 4,700 Angstroms. The resist layer 80 is patterned, forexample, to a minimum line with critical dimension (CD) of between about0.151 microns and 0.169 microns.

Referring now to FIG. 10, several important features of the presentinvention are presented. The semiconductor wafers are loaded into thedry etching chamber as outlined in the process flow step 50. In thepreferred process example, the dry plasma etching chamber comprises anApplied Materials DPS-POLY system. The overall dry plasma etching recipesequence, shown as step 50 of FIG. 8, comprises a series of recipesteps. Each recipe step completes a step in the process of transferringthe resist layer pattern into the polysilicon layer.

The first recipe step comprises the trim etch. As in the prior artprocess, the trimming step is not considered an essential aspect of themethod of the present invention. In the trimming etch, the resist layer80 is etched to reduce the line widths of the resist layer 80. In theexample process, the minimum pre-trim resist layer 80 width is betweenabout 0.151 microns and 0.169 microns. The final after etch polysiliconCD is specified at between about 0.145 microns and 0.125 microns. Sincethe final polysilicon CD is about 0.025 microns less than the availableresist CD, it is necessary to trim back the width of the resist layer80.

The trimming etch recipe preferably comprises a combination of gases. Inthe preferred embodiment, HBr gas is flowing at a rate of between about60 sccm and 100 sccm, Ar gas is flowing at a rate of between about 40sccm and 80 sccm, and 0 ₂ gas is flowing at a rate of between about 2sccm and 10 sccm. The chamber pressure is between about 4 milliTorr and15 milliTorr. A source power of between about 200 Watts and 400 Wattsand a bias power of between about 40 Watts and 80 Watts are used. Thetrimming etch is performed for between about 20 seconds and 60 seconds.The trimming etch reduces the width of the resist layer 80 prior totransferring the pattern to the hard mask layer 72.

Following the trim etch, the hard mask layer 72 is etched. If thesilicon dioxide layer 76 is used, it is etched with the hard mask layer.The hard mask etch comprises a combination of gases. In the preferredembodiment, CF₄ gas is flowing at a rate of between about 10 sccm and 30sccm and Ar gas is flowing at a rate of between about 140 sccm and 160sccm. The chamber pressure is maintained at between about 8 milliTorrand 12 milliTorr. The source power is controlled at between about 550Watts and 650 Watts while the bias power is controlled at between about40 Watts and 80 Watts. The hard mask layer 72 is etched using anendpoint detection that detects when the hard mask layer 72 has beenetched through.

Following the hard mask etch, the resist layer 80 is stripped away. Theability to perform this step within the same dry etch plasma chamber isan important feature of the present invention. The resist layer 80 isremoved by flowing O₂ gas at a rate of between about 40 sccm and 60sccm. A chamber pressure of between about 4 milliTorr and 15 milliTorris maintained. The source power is controlled at between about 30 Wattsand 500 Watts, while the bias power is controlled at between about 80Watts and 100 Watts. The strip is stopped using an endpoint detectionthat detects that the photoresist layer 80 is no longer present.

Following the resist strip step, it is likely that organic polymerresidue remains from the photoresist material. This residue will coatthe interior of the dry plasma etching chamber and may adhere to thesidewalls of the hard mask 72 and 76 as shown by 84 in FIG. 10. It iscritical to the method of the present invention that the resiststripping step be followed by a polymer cleaning step. The polymer cleanremoves any organic polymer residue from the chamber and from thesidewalls of the hard mask 72 and 76.

The polymer clean step is accomplished by flowing CF₄ gas at a rate ofbetween about 60 sccm and 100 sccm. The chamber pressure is maintainedat between about 4 milliTorr and 15 milliTorr. The source power iscontrolled at between about 300 Watts and 500 Watts, while the biaspower is controlled at between about 30 Watts and 50 Watts. The polymerclean is performed for between about 5 seconds and 15 seconds. Thepolymer cleaning step keeps the chamber clean prior to each polysiliconetch process.

Referring now to FIG. 11, the polysilicon layer 68 is now etched usingtwo recipe steps comprising, first, a main etch (ME) and, second, anoveretch (OE). In the main etch, the polysilicon layer 68 is etchedusing a gas combination of HBr, Cl₂, and He—O₂. The main etch is stoppedusing an endpoint detection method that detects when the polysiliconlayer 68 has been etched through. The overetch recipe uses a gascombination of HBr and He—O₂ for a controlled time period to insure thatthe remaining polysilicon layer 68 will be free of stringers and shorts.

The main etch comprises HBr flowing at a rate of between about 160 sccmand 200 sccm, Cl₂ flowing at a rate of between about 10 sccm and 30sccm, and He—O₂ flowing at a rate of between about 2 sccm and 10 sccm.The chamber pressure is maintained at between about 4 milliTorr and 15milliTorr. The source power is controlled at between about 550 Watts and650 Watts. The bias power is controlled at between about 30 Watts and 50Watts.

The overetch recipe comprises HBr flowing at a rate of between about 130sccm and 150 sccm and He—O₂ flowing at a rate of between about 4 sccmand 6 sccm. The chamber pressure is maintained at between about 60milliTorr and 100 milliTorr. The source power is controlled at betweenabout 300 Watts and 500 Watts, while the bias power is controlled atbetween about 60 Watts and 80 Watts. The overetch is performed forbetween about 60 seconds and 100 seconds. Following the polysiliconetch, the device cross-section appears as shown in FIG. 11. The silicondioxide layer 76 is etched away during the polysilicon etch step.

Referring now to FIG. 12, the hard mask is stripped away to complete thepatterning of the polysilicon layer 68. The wafers are removed from thedry plasma etch chamber to perform the hard mask strip. In the preferredembodiment, the hard mask layer 72 comprises silicon oxynitride. Thissilicon oxynitride layer 72 is preferably removed using a wet etchcomprising H₃PO₄.

The method of the present invention, using the in-situ stripping of thephotoresist layer, has been demonstrated on a 0.15 micron process. Themethod demonstrates stable after etch inspection (AEI) CD performance.The three-sigma variation is between about 4 nanometers and 8nanometers. SEM and X-SEM profiles, after polysilicon gate etching,demonstrate excellent vertical profiles with no pitting, trenching, orresidue problems. In addition, the method saves about 4 hours comparedto the prior art approach.

As shown in the preferred embodiments, the present invention provides avery manufacturable process for patterning the polysilicon layer in anintegrated circuit device. The present invention saves cycle time andreduces costs. The present invention has been successfully demonstratedon a 0.15 micron process. The novel approach allows photoresist to bestripped away in the dry plasma etch chamber. The polymer cleaning stepeliminates problems associated with resist residue build-up in thechamber or on hard mask sidewalls.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A method to pattern a polysilicon layer in the manufacture of anintegrated circuit device comprising: providing a polysilicon layeroverlying a semiconductor substrate; providing a hard mask layeroverlying said polysilicon layer; providing a resist layer overlyingsaid hard mask layer; patterning said resist layer to form a resist maskthat exposes a part of said hard mask layer; patterning said polysiliconlayer wherein said patterning is performed sequentially in a dry plasmaetch chamber and wherein said patterning comprises: etching said hardmask layer exposed by said resist mask to form a hard mask that exposesa part of said polysilicon layer; thereafter stripping away said resistmask; thereafter cleaning away polymer residue from said hard maskwherein said cleaning away comprises a chemistry containing CF₄ gas; andthereafter etching said polysilicon layer exposed by said hard mask; andstripping away said hard mask to complete the patterning of saidpolysilicon layer in the manufacture of the integrated circuit device.2. The method according to claim 1 wherein said hard mask layercomprises silicon oxynitride.
 3. The method according to claim 1 whereinsaid step of etching said hard mask layer comprises a chemistrycontaining CF₄ gas.
 4. The method according to claim 1 wherein said stepof stripping away said resist mask comprises a chemistry containing O₂gas.
 5. The method according to claim 1 wherein said step of etchingsaid polysilicon layer comprises a main etch step followed by anoveretch step.
 6. The method according to claim 1 wherein said step ofetching said polysilicon layer comprises a chemistry of: HBr gas, Cl₂gas, He—O₂ gas, and combinations thereof.
 7. The method according toclaim 1 further comprising providing a silicon dioxide layer overlyingsaid hard mask layer and underlying said resist layer.
 8. The methodaccording to claim 1 further comprising etching said resist layer totrim said resist layer prior to said step of etching said hard masklayer wherein said etching of said resist layer is performed in said dryplasma etching chamber.
 9. The method to pattern a polysilicon layer inthe manufacture of an integrated circuit device comprising: providing apolysilicon layer overlying a semiconductor substrate; providing a hardmask layer overlying said polysilicon layer; providing a silicon dioxidelayer said hard mask layer; providing a resist layer overlying said hardmask layer; patterning said resist layer to form a resist mask thatexposes a part of said hard mask layer; patterning said polysiliconlayer wherein said patterning is performed sequentially in a dry plasmaetch chamber and wherein said patterning comprises: etching said resistmask to trim said resist mask; thereafter etching said hard mask layerexposed by said resist mask to form a hard mask that exposes a part ofsaid polysilicon layer; thereafter stripping away said resist mask;thereafter cleaning away polymer residue from said resist mask whereinsaid cleaning away comprises a chemistry containing CF₄ gas; andthereafter etching said polysilicon layer exposed by said hard mask; andstripping away said hard mask to complete the patterning of saidpolysilicon layer in the manufacture of the integrated circuit device.10. The method according to claim 9 wherein said hard mask layercomprises silicon oxynitride.
 11. The method according to claim 9wherein said step of etching said resist mask to trim said resist maskcomprises a chemistry containing O₂ gas.
 12. The method according toclaim 9 wherein said step of etching said hard mask layer comprises achemistry of CF₄ gas.
 13. The method according to claim 9 wherein saidstep of stripping away said resist layer comprises a chemistrycontaining O₂ gas.
 14. The method according to claim 9 wherein said stepof etching said polysilicon layer comprises a main etch step followed byan overetch step.
 15. The method according to claim 9 wherein said stepof etching said polysilicon layer comprises a chemistry of: HBr gas, Cl₂gas, He—O₂ gas, and combinations thereof.
 16. A method to pattern apolysilicon layer in the manufacture of an integrated circuit devicecomprising: providing a gate oxide overlying a semiconductor substrate;providing a polysilicon layer overlying said gate oxide layer; providinga silicon oxynitride layer overlying said polysilicon layer; providing asilicon dioxide layer overlying said silicon oxynitride layer; providinga resist layer overlying said silicon dioxide layer; patterning saidresist layer to form a resist mask that exposes a part of said silicondioxide layer; patterning said polysilicon layer wherein said patterningis performed sequentially in a dry plasma etch chamber and wherein saidpatterning comprises: etching said resist mask to trim said resist mask;thereafter etching said silicon dioxide layer and said siliconoxynitride layer exposed by said resist mask to form a hard mask thatexposes a part of said polysilicon layer; thereafter stripping away saidresist mask; thereafter cleaning away polymer residue from said resistmask wherein said cleaning away comprises a chemistry containing CF₄gas; and thereafter etching said polysilicon layer exposed by said hardmask wherein said etching comprises a main etch step followed by anoveretch step; and stripping away said hard mask to complete thepatterning of said polysilicon layer in the manufacture of theintegrated circuit device.
 17. The method according to claim 16 whereinsaid step of etching said silicon dioxide layer and said siliconoxynitride layer comprises a chemistry of CF₄ gas.
 18. The methodaccording to claim 16 wherein said step of stripping away said resistlayer comprises a chemistry containing O₂ gas.
 19. The method accordingto claim 16 wherein said step of etching said polysilicon layercomprises a chemistry of: HBr gas, Cl₂ gas, He—O₂ gas, and combinationsthereof.
 20. A method of forming a semiconductor device, the methodcomprising: providing a semiconductor substrate with a conductive layerformed thereon; providing a hard mask layer above said conductive layer,said hard mask layer comprising silicon oxynitride; providing a bufferlayer above said hard mask layer; providing a resist layer above saidbuffer layer; patterning said resist layer to form a resist mask thatexposes a part of said buffer layer; and patterning said conductivelayer in a dry plasma etch chamber, said patterning comprising: etchingsaid hard mask layer and said buffer layer exposed by said resist maskto form a hard mask that exposes a part of said conductive layer;thereafter stripping away said resist mask; and thereafter etching saidconductive layer exposed by said hard mask.
 21. The method of claim 20wherein said buffer layer comprises an oxide.
 22. The method of claim 20wherein said buffer layer comprises silicon dioxide.
 23. The method ofclaim 20 wherein said step of etching said hard mask layer comprises achemistry containing CF₄ gas.
 24. The method of claim 20 wherein saidstep of etching said conductive layer comprises a main etch stepfollowed by an overetch step.
 25. The method of claim 20 furthercomprising etching said resist layer to trim said resist layer prior tosaid step of etching said hard mask layer wherein said etching of saidresist layer is performed in said dry plasma etch chamber.
 26. A methodfor forming a semiconductor device, the method comprising: providing apolysilicon layer overlying a semiconductor substrate; providing a hardmask layer overlying said polysilicon layer; providing a resist layeroverlying said hard mask layer; patterning said resist layer to form aresist mask that exposes a part of said hard mask layer; and patterningsaid polysilicon layer in a dry plasma etch chamber and wherein saidpatterning comprises: etching said hard mask layer exposed by saidresist mask to form a hard mask that exposes a part of said polysiliconlayer; stripping away said resist mask in a first process step; removingpolymer residue resulting from said stripping step in a second processstep; and etching said polysilicon layer exposed by said hard mask. 27.The method of claim 26 wherein the step of patterning said polysiliconlayer includes stripping away said hard mask.
 28. The method of claim 26further comprising cleaning away polymer residue from said hard maskafter stripping away said resist mask.
 29. The method of claim 26wherein said hard mask layer comprises silicon oxynitride.
 30. Themethod of claim 26 wherein the step of etching said hard mask layercomprises a chemistry containing CF₄ gas.
 31. The method of claim 26wherein said step of etching said polysilicon layer comprises a mainetch step followed by an overetch step.
 32. The method of claim 26further comprising etching said resist layer to trim said resist layerprior to said step of etching said hard mask layer wherein said etchingof said resist layer is performed in said dry plasma etch chamber.
 33. Amethod for forming a semiconductor device, the method comprising:providing a wafer having a substrate, a first layer formed on thesubstrate, a hard mask layer formed on the first layer, a buffer layerformed on said hard mask layer, and a resist layer formed on the bufferlayer; patterning said hard mask layer and said buffer layer to form ahard mask that exposes a part of said first layer; removing said resistlayer; and patterning said first layer by etching said first layer andremoving said hard mask layer and said buffer layer.
 34. The method ofclaim 33 wherein the steps of patterning said hard mask layer, removingsaid resist layer, and patterning said first layer are performed in adry plasma etch chamber.
 35. The method of claim 33 wherein the step ofpatterning said hard mask layer includes etching the hard mask layer andthe buffer layer.
 36. The method of claim 35 wherein said step ofetching said hard mask layer comprises a chemistry containing CF₄ gas.37. The method of claim 33 wherein said step of etching said first layercomprises a main etch step followed by an overetch step.
 38. The methodof claim 33 wherein the step of patterning said hard mask layer includespatterning a resist layer.
 39. The method of claim 38 further comprisingetching said resist layer to trim said resist layer prior to said stepof etching said hard mask layer wherein said etching of said resistlayer is performed in said dry plasma etch chamber.
 40. The method ofclaim 33 wherein said hard mask layer comprises silicon oxynitride. 41.The method of claim 33 wherein said buffer layer comprises an oxide. 42.The method of claim 33 wherein said buffer layer comprises silicondioxide.
 43. A method of forming a semiconductor device, the methodcomprising: providing a semiconductor substrate with a conductive layerformed thereon; providing a hard mask layer above said conductive layer;providing a resist layer above said hard mask layer; patterning saidresist layer to form a resist mask that exposes a part of said hard masklayer; and patterning said conductive layer in a dry plasma etchchamber, said patterning comprising: etching said hard mask layerexposed by said resist mask to form a hard mask that exposes a part ofsaid conductive layer; thereafter stripping away said resist mask usinga first chemistry; thereafter removing polymer residue using a secondchemistry different from the first chemistry; and thereafter etchingsaid conductive layer exposed by said hard mask.
 44. The method of claim43 wherein said hard mask layer comprises silicon oxynitride.
 45. Themethod of claim 43 wherein said step of etching said hard mask layercomprises a chemistry containing CF₄ gas.
 46. The method of claim 43wherein said step of etching said conductive layer comprises a main etchstep followed by an overetch step.
 47. The method of claim 43 furthercomprising etching said resist layer to trim said resist layer prior tosaid step of etching said hard mask layer wherein said etching of saidresist layer is performed in said dry plasma etch chamber.
 48. A methodfor forming a semiconductor device, the method comprising: providing awafer having a substrate, a first layer formed on the substrate, a hardmask layer formed on the first layer, a buffer layer formed on said hardmask layer, and a resist layer formed on the buffer layer; patterningsaid hard mask layer to form a hard mask that exposes a part of saidfirst layer; removing said resist layer; and patterning said first layerby etching said first layer and removing said hard mask layer.
 49. Themethod of claim 48 wherein the steps of patterning said hard mask layer,removing said resist layer, and patterning said first layer areperformed in a dry plasma etch chamber.
 50. The method of claim 48wherein the step of patterning said hard mask layer includes etching thehard mask layer.
 51. The method of claim 50 wherein said step of etchingsaid hard mask layer comprises a chemistry containing CF₄ gas.
 52. Themethod of claim 48 wherein said step of etching said first layercomprises a main etch step followed by an overetch step.
 53. The methodof claim 48 wherein the step of patterning said hard mask layer includespatterning a resist layer.
 54. The method of claim 53 further comprisingetching said resist layer to trim said resist layer prior to said stepof etching said hard mask layer wherein said etching of said resistlayer is performed in said dry plasma etch chamber.
 55. The method ofclaim 48 wherein said hard mask layer comprises silicon oxynitride.